run: 
	{
		file_prefix 	= "CalibrationTest";
  		time_preset_sec = 600;
  		event_preset 	= 550;
  		polling_wait_ms = 5; // not used
   		binary_out 	= 1; // old ???
    		test_mode 	= 0; // old ???
	}; // end run


//
// Default configuration file
//

default:
{
	
	trigger:
	{
		hit_en0		= 0xFFFFFF;
   		hit_en1		= 0xFFFFFF;
   		hit_en2		= 0xFFFFFF;

		hiten =[0xFFFFFF,0xFFFFFF,0xFFFFFF]
	}
	
	VME:
	{
		vme_enable 	= 0;
		v792n_addr 	= 0x990000;
		scaler_limit 	= 1023;
	};
	cb: 
	{ 
		fe: 
  		{
			cfgReg1:
			{
				auto_trigger 	= 0;	// old??
     				test_en_eve 	= 0;
    				test_en_odd 	= 0;
				hold1_delay 	= 255;  // Actual delay = 11.5[ns] + hold1_delay * 1.0 [ns]  
     				initial_out_ch 	= 0; 
				en_auto_trig	= 0;	// SELF TRIGGER
				en_ext_trig 	= 1;	// EXTERNAL TRIGGER 
				en_zero_supp 	= 0;	//old??
				one_sixtyfour 	= 0;
				led0 		= 0;
				led1 		= 0;
			}
			cfgReg2:
			{
				Daq_mode 	= 0; 	// 0 = ALL, 1 = HIT enabled, 2 = Over THR, 3 = none 
				hit_delay 	= 1;	// 3 bit, 25 ns step
				TrigMode 	= 0; 	// 0 = Fast-or, 1 =Mult. Internal Trigger (algorithm choice) 
				StartDaqDelay	= 10; //  StartSettlingTime // before 2011/10/12 was 11
     				FastSettlingTime=  6;			
      				SlowSettlingTime= 30;
			}

     			maroc_revision = 3;	//  INUTILE LO FGA IL SOWTWARE


   			channel_enabled_start 	= 0;  // old??
   			channel_enabled_stop 	= 63; // old??

			// SPARSE READ OUT 

    			daq_thr_def 	= 1680;	// Soglia default di Sparse Read Out 
						// (valori maggiori vengono trasferiti, se daq_mode = 2)

						// daq_thr63	= 2000  //  Soglia di ReadOut per uno specifico canale
						// daq_thr62	= 1500
						// daq_thr7	= 1502
						// daq_thr10	= 1503
     			mrc2: 
     			{
      				en_ck 		= 1;
       				cmd_lvds 	= 0;
       				en_serializer 	= 0;
       				cmd_lucid 	= 0;
       				fs_choice 	= 1;
       				sw_20f 		= 0;
       				sw_40f 		= 0;
       				sw_25k 		= 0;
       				sw_50k 		= 0;
       				sw_100k 	= 0;
       				sw_50f 		= 0;
       				sw_100f 	= 0;
       				en_adc 		= 0;
       				h1h2_choice 	= 0;
      				valid_ch_select = 1;
       				swss_c2 	= 0;
       				swss_c1 	= 0;
       				swss_c0 	= 0;
				
				gain_default	=32;
				
				dac:
				{
					dac0 	= 0x000;	// 0x800002 FOR MAROC2 are out of linear range! Moreover dac0 (the only DAC used) is set by thr parameters, not by this 
       					dac1 	= 0x000	;	// 0x805501 FOR MAROC2
       					dac2 	= 0x000	;	// 0x80ff01 FOR MAROC2
				}
			}; 

       			mrc3:  
       			{
				DAC0 = 100;
				DAC1 = 200;
				preamp:
				{
					gain_default = 64; // // default gain if gain_map does not exist

					cmd_ss 		= 1; 	// enable signal at the  SS inputs.Should be ON if you want to DO CHARGE MEASUREMENTS
           				cmd_fsb 	= 1;	// enable signal at the FSB inputs.Should be ON if you want to USE FSB1 or FSB2
           				cmd_fsu 	= 1;	// enable signal at the FSU inputs.Should be ON if you want to  use FSU
				};
				slowpath:
				{
					buffer: 
					{
						swb_buf_250f 	= 0;	
       						swb_buf_500f 	= 0;	
       						swb_buf_1p 	= 1;
       						swb_buf_2p 	= 0;
					}	
					shaper:
					{
       						enable_ss 	= 1;	
       			 			sw_ss_300f 	= 1;	 
       						sw_ss_600f 	= 0;	 
       						sw_ss_1200f 	= 0;
					}
				}
				fastpath:
				{
					general:
					{
	   					d1_d2 		= 0;		// if 0 trigger from FSB1 and DAC0, if 1 trigger from FSB2 and DAC1
	  					polar_discri 	= 0;		// if 0 High polarity of the trigger output // if 1 Low  polarity of the trigger output
           					enb_tristate 	= 1;		// Enable all trigger outputs. Should be ON to see trigger outputs
	  					cmd_fsb_fsu 	= 0;		// Choice between FSB1 or FSU for the first discri input (with DAC0), if 0 = FSB, if 1 = FSU
						small_dac 	= 1;		// to decrease the slop of DAC0 (better accuracy)
					}
					fsu:
					{
    						sw_fsu_100k 	= 0;
		 				sw_fsu_50k 	= 0;
		 				sw_fsu_25k 	= 0;
						sw_fsu_40f 	= 1;		// better if ON	
	 					sw_fsu_20f 	= 1;		// better if ON
					}	
					fsb1:
					{
	 					sw_fsb1_50f 	= 1;		// better if ON		
	 					sw_fsb1_100f 	= 1;		// better if ON		
	 					sw_fsb1_100k 	= 0;	
	 					sw_fsb1_50k 	= 0;
					}	
					fsb2: // Half Gain 
					{
         					sw_fsb2_50f 	= 1;		// better if ON		
	 					sw_fsb2_100f 	= 0;	
	 					sw_fsb2_100k 	= 0;	
	 					sw_fsb2_50k 	= 0;
					}				
					dc:
					{
	   					valid_dc_fsb2	= 0;		// enable FSB2 DC measurements
	   					valid_dc_fs 	= 1;		// enable FSB and FSU DC measurements
					}
				}
				adc:
				{
					h1h2_choice 	= 0;	// choice between first and second T&H for the input of the ADC
       					en_adc 		= 0; 	// enable ADC conversion inside the ASIC (ON to make the conversion)
								// Wilkinson ADC parameters
           				enb_out_adc 	= 1;	// to use the Wilkinson ADC should be off
	   				inv_start_gray 	= 1;	// to use the Wilkinson ADC should be off
	   				ramp_8bit 	= 0;
	   				ramp_10bit 	= 0;
	   				inv_discri_adc 	= 0;	// ADC discri output could be inverted (Should be OFF)

				}
				others:
				{
	  				en_otabg 	= 0;		// Power pulsing bit for bandgap (not active on MAROC3 test board)		
 	  				en_dac 		= 0;		// Power pulsing bit for DACs    (not active on MAROC3 test board)
	  				cmd_ck_mux 	= 0;		// should be off 
				}
        		}; // close m3_ext
  		}; // end card
	}; // end controller	
};// end default
