The FPGA Developers’ Forum (FDF) is a platform to discuss and exchange information, experiences, implementation ideas, tips, and tricks as well as challenges faced with design tools, specific FPGA technologies.
The 1st FDF meeting will take place at CERN on 11-13 June 2024. We will discuss topics like:
- Sharable HDL cores, that can be used in any FPGA design
- Algorithm implementation in HDL and HLS (Neural Networks, Transforms, or any other algorithm)
- Solutions to everyday digital design problems (Multiple MGT configuration, Clock Domain Crossing methods, Super Logic Region Crossing, NoC, and more)
- HDL verification and simulation tools (simulation, emulation, and more)
- HDL development tools (code management, continuous integration, register mapping, package generations, and more)
There is no registration fee, you’re very welcome to participate in the FDF meeting even if you’re not giving a talk either online or in person. And remember that FDF is open to anyone, not only CERN users, simply go to the event page (www.cern.ch/fdf) and register to the event.
The FDF aims to form a topical community of digital designers — especially on FPGAs — working in physics and beyond, and to discuss details that very rarely see the light of day in typical workshops in our field.
We will focus on the ‘how’ digital designs are implemented rather than their scientific end-goal, and novelty is not the only criterion. Sharing tips on how to avoid pitfalls, or other ideas and recommendations that could save your colleagues precious time, are considered equally important.
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